---------------------------------------------------------------------------------
  -- Design Name : EX+MEM / WB Registers
  -- File Name   : R_ExMem_Wb.vhd
  -- Function    : EX+MEM / WB Registers
  -- Authors     : Mirko Francuski  2006/0225
  --               Milos Mihajlovic 2006/0039
  -- School      : University of Belgrade
  --               School for Electrical Engineering
  --               Department for Computer Engineering and Information Theory
  -- Subject     : VLSI Computer Systems
---------------------------------------------------------------------------------

library ieee;

use ieee.std_logic_1164.all;
use ieee.std_logic_signed.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
use work.UserPkg.all;

entity R_ExMem_Wb is
  port (
    clk          : in  std_logic;
    reset        : in  std_logic;
    stall        : in  std_logic;
    wrkIn        : in  std_logic;
    wrkOut       : out std_logic;
    aluDataIn    : in  word32;
    aluDataOut   : out word32;
    stackDataIn  : in  word32;
    stackDataOut : out word32;
    rdIn         : in  regAddr;
    rdOut        : out regAddr;
    opIn         : in  opCode;
    opOut        : out opCode
  );
end R_ExMem_Wb;

architecture behavioral of R_ExMem_Wb is
  signal aluDataRegIn     : word32;
  signal aluDataRegOut    : word32;
  signal stackDataRegIn   : word32;
  signal stackDataRegOut  : word32;
  signal instIn           : word32;
  signal instOut          : word32;
  signal zero             : std_logic_vector(LEN_WORD - 1 downto 12);
  signal ld               : std_logic;
  signal workSignal       : std_logic;
  
begin

  aluDataRegIn   <= aluDataIn;
  aluDataOut     <= aluDataRegOut;
  stackDataRegIn <= stackDataIn;
  stackDataOut   <= stackDataRegOut;  
  
  zero         <= (others => '0');
  instIn       <= zero & wrkIn & rdIn & opIn   when reset = '0' else
                  (5 downto 0 => '1', others => '0'); --zeros & OPC_NOP;
                   
  opOut        <= instOut( 5 downto 0);
  rdOut        <= instOut(10 downto 6);  
  workSignal   <= instOut(11);
  wrkOut       <= workSignal;
  
  ld <= wrkIn or workSignal;
  
  inst: GenReg32 port map ( 
    clk    => clk,
    ld     => ld or reset,
    cl     => '0',
    regIn  => instIn,
    regOut => instOut
  );
  
  aluData: GenReg32 port map ( 
    clk    => clk,
    ld     => ld,
    cl     => reset,
    regIn  => aluDataRegIn,
    regOut => aluDataRegOut
  );
  
  stackData: GenReg32 port map ( 
    clk    => clk,
    ld     => ld,
    cl     => reset,
    regIn  => stackDataRegIn,
    regOut => stackDataRegOut
  );
    
end architecture behavioral;